The present invention relates to the field of semiconductor processing and metal interconnection technology, and more particularly, to formation of a dual damascene metal interconnect structure in low k dielectric layers.
The escalating requirements for high density and performance associated with ultra large-scale integration semiconductor wiring require responsive changes in interconnection technology. These escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnection pattern, particularly where sub-micron via contacts and trenches have high aspect ratios imposed by miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally of doped monocrystalline silicon, and a plurality of sequentially formed dielectric layers and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by inter-wiring spacings. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontally with respect to the semiconductor substrate. Semiconductor chips comprising five or more levels of metallization are becoming more prevalent as device geometries shrink to sub-micron levels.
A conductive plug filling a via hole is typically formed by depositing a dielectric interlayer on a conductive layer comprising at least one conductive pattern, forming an opening in the dielectric layer by conventional photolithographic and etching techniques and filling the opening with conductive material, such as tungsten (W). Excess conductive material on the surface of the dielectric layer is typically removed by chemical mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the dielectric interlayer and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section, which opening is filled with conductive material, typically a metal, to simultaneously form a conductive plug and electrical contact with a conductive line.
In efforts to improve the operating performance of a chip, low k dielectric materials have been increasingly investigated for use as replacements for dielectric materials with higher k values. Lowering the overall k value of the dielectric layers employed in the metal interconnect layers lowers the RC of the chip and improves its performance. However, low k materials such as benzocyclobutene (BCB), hydrogen silsesquioxane (HSQ), SiOF, etc., are often more difficult to handle than traditionally employed higher k materials, such as an oxide. For example, low k dielectric materials are readily damaged by techniques used to remove photoresist materials after the patterning of a layer. Hence, a feature formed in a low k dielectric layer may be damaged when the photoresist layer used to form the feature (e.g., trench or via) is removed.
Another problem with low k dielectric materials, especially porous low k dielectric materials, is their relatively low mechanical strength. This can lead to a number of concerns in the final product, since the relatively low mechanical strength of the porous low k dielectric material can exhibit stresses and cracking that reduces the structural integrity of the layer and possibly subsequent layers that are formed over the porous dielectric layer. The low mechanical strength of the porous low k dielectric material is especially noticed in via layers. This is because the metal density in via layers is low in comparison to conductive line layers. Even moderately strong porous low k dielectric materials may not adequately survive the chemical mechanical polishing process during which pressure is applied against the top surface of the wafer. Hence, since the metal density in the via layers is low, CMP pressure applied may cause the porous low dielectric material to mechanically fail.
There is a need for forming a metal interconnect structure using a dual damascene technique that employs porous low k dielectric materials in the dielectric layers of the structure. At the same time, however, there is a need to improve the mechanical strength of such an arrangement.
These and other needs are met by embodiments of the present invention which provide a method of forming a metal interconnect structure, comprising the steps of forming a first porous low k dielectric layer on a substrate. Dielectric studs are formed in the first porous low k dielectric layer. The dielectric studs comprise a dense low k dielectric material. A second porous low k dielectric layer is formed on the first porous low k dielectric layer. A trench is then etched in the second porous low k dielectric layer and a via in the first porous low k dielectric layer is etched. The via is etched from one of the dielectric studs. The trench is located over the via. Conductive material is simultaneously deposited in the via and the trench to form a conductive plug and line.
The formation of dielectric studs in a porous low k dielectric layer, such as a via layer, improves the mechanical strength of the dual damascene metal interconnect arrangement. This allows porous low k dielectric material to be used in the via and trench layers, with improved mechanical strength in the arrangement. A via fill technique is employed in certain embodiments of the present invention in which the dielectric studs are formed by etching holes in the porous low k dielectric layer and filling these holes with dense low k dielectric material. The use of dense low k dielectric material increases the mechanical strength of the porous low k dielectric layer. When a conductive plug is to be formed, some of the dielectric studs are etched when the trench in the overlying electric layer is etched. One of the advantages of using a via fill technique is that any damage to the via holes in the via layer caused by photoresist removal processes is lessened.
The earlier stated needs are also met by other aspects of the present invention which provide a metal interconnect structure comprising a first porous low k dielectric layer and at least one dielectric plug in the first porous low k dielectric layer. This dielectric plug comprises dense low k dielectric material. A second porous low k dielectric layer is provided on the first porous low k dielectric layer. A conductive line is provided in the second porous low k dielectric layer and a conductive plug in the first porous low k dielectric layer. The conductive line overlies the conductive plug and together forms an interfaceless dual damascene conductive structure.
The foregoing and other features, aspects and advantages of the present invention will become apparent from the following detail description of the present invention when taken in conjunction with the accompanying drawings.